1. Field of the Invention
This invention relates generally to integrated circuit testing and, in particular, to automated optimization of timing and high-speed interface settings for a programmable logic device.
2. Description of the Related Art
Typically, a programmable logic device (PLD) design is optimized for timing and interface settings through a labor-intensive process, which analyzes off-chip signals. The results of this optimization may be used to develop a specification to guide a customer utilizing the PLD. As the sophistication of these devices is becoming greater, the optimization process is becoming more involved. In addition, the test equipment used to analyze the off-chip signals must keep pace with the sophistication of the devices being tested. Of course, this results in an increased cost for the test equipment as the algorithms and scripts need to be developed to handle the testing of all the capabilities of the device being tested.
One of the shortcomings of the testing through off-chip signals is that the test equipment acts as a source, i.e., provides the stimulation, and an analyzer, i.e., interprets the resulting signal responsive to the stimulation. This requirement certainly adds to the cost of the test equipment. Moreover, the occurrence of rapid technological change prevents the test equipment from being able to test all the capabilities of more advanced integrated circuit designs.
Another shortcoming of tile off chip test equipment is that the signal sent to the device from the off-chip test equipment requires monitoring. That is the signal level, quality, timing, and termination, especially when dealing with data rates of multiple hundreds of megabits per second, are call critical factors handled by the test equipment in order to analyze the chip performance. Failure to adequately protect the signal will result in having to repeat the test, which further delays the process.
As a result, there is a need to solve the problems of the prior art to more effectively optimize timing and high speed interface settings for a programmable logic device.